Name: ISSI IS43R16320D-5TL
Brand: ISSI
SKU: 870-IS43R16320D-5TL
Price: 7.86 USD
Availability: InStock

Description:

DRAM 512M (32Mx16) 200MHz 2.5v DDR SDRAM

ECAD Model:

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Pricing (USD)

Qty.	Unit Price	Ext. Price
	$7.86	$7.86
	$7.32	$73.20
	$7.10	$177.50
	$6.93	$346.50
	$6.76	$730.08

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Product Attribute	Attribute Value	Select Attribute
Manufacturer:	ISSI
Product Category:	DRAM
RoHS:
Type:	SDRAM - DDR
Memory Size:	512 Mbit
Data Bus Width:	16 bit
Maximum Clock Frequency:	200 MHz
Package/Case:	TSOP-II-66
Organisation:	32 M x 16
Access Time:	5 ns
Supply Voltage - Min:	2.3 V
Supply Voltage - Max:	2.7 V
Minimum Operating Temperature:	0 C
Maximum Operating Temperature:	+ 70 C
Series:	IS43R16320D
Packaging:	Tray
Brand:	ISSI
Country of Assembly:	Not Available
Country of Diffusion:	Not Available
Country of Origin:	CN
Moisture Sensitive:	Yes
Mounting Style:	SMD/SMT
Product Type:	DRAM
Factory Pack Quantity:	108
Subcategory:	Memory & Data Storage
Supply Current - Max:	430 mA

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Datasheet

IS43R16320D-5TL Datasheet (PDF)

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CNHTS:: 8542319090
USHTS:: 8542320028
JPHTS:: 8542320216
KRHTS:: 8542321010
MXHTS:: 8542320299
ECCN:: EAR99

DDR SDRAM

ISSI 512-Mbit DDR SDRAM achieves high-speed data transfer using pipeline architecture and two data word accesses per clock cycle. The 536,870,912-bit memory array is internally organized as four banks of 128Mb to allow concurrent operations. The pipeline allows Read and Write burst accesses to be virtually continuous, with the option to concatenate or truncate the bursts. The programmable features of burst length, burst sequence, and CAS latency enable further advantages. The device is available in 8-bit, 16-bit, and 32-bit data word sizes. Input data is registered on the I/O pins on both edges of Data Strobe signal(s), while output data is referenced to both edges of Data Strobe and both edges of CLK. ISSI 512-Mbit DDR SDRAM commands are registered on the positive edges of CLK.

IS43R32800D 8Mx32 256-Mbit DDR SDRAM

ISSI IS43R32800D 8Mx32 256-Mbit DDR SDRAM achieves high-speed data transfer using pipeline architecture and two data word accesses per clock cycle. The 268,435,456-bit memory array is internally organized as four banks of 64MB to allow concurrent operations. The pipeline allows Read and Write burst accesses to be virtually continuous, with the option to concatenate or truncate the bursts. The programmable features of burst length, burst sequence, and CAS latency enable further advantages.