IS43R16320D-6BLI

ISSI
870-IS43R16320D-6BLI
IS43R16320D-6BLI

Mfr.:

Description:
DRAM 512M (32Mx16) 166MHz 2.5v DDR SDRAM

Datasheet:
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Availability

Stock:
Non-Stocked
Factory Lead Time:
Minimum: 1   Multiples: 1
Unit Price:
$-.--
Ext. Price:
$-.--
Est. Tariff:

Pricing (USD)

Qty. Unit Price
Ext. Price
$13.26 $13.26
$12.31 $123.10
$11.94 $298.50
$11.65 $582.50
$11.37 $1,137.00
$11.00 $2,090.00
$10.72 $6,110.40
$10.45 $11,913.00
2,660 Quote

Product Attribute Attribute Value Select Attribute
ISSI
Product Category: DRAM
RoHS:  
SDRAM - DDR
512 Mbit
16 bit
166 MHz
BGA-60
32 M x 16
6 ns
2.3 V
2.7 V
- 40 C
+ 85 C
IS43R16320D
Tray
Brand: ISSI
Country of Assembly: Not Available
Country of Diffusion: Not Available
Country of Origin: TW
Moisture Sensitive: Yes
Mounting Style: SMD/SMT
Product Type: DRAM
Factory Pack Quantity: 190
Subcategory: Memory & Data Storage
Supply Current - Max: 370 mA
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Attributes selected: 0

Datasheet

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CNHTS:
8542319090
USHTS:
8542320028
JPHTS:
8542320216
KRHTS:
8542321010
MXHTS:
8542320299
ECCN:
EAR99

DDR SDRAM

ISSI 512-Mbit DDR SDRAM achieves high-speed data transfer using pipeline architecture and two data word accesses per clock cycle. The 536,870,912-bit memory array is internally organized as four banks of 128Mb to allow concurrent operations. The pipeline allows Read and Write burst accesses to be virtually continuous, with the option to concatenate or truncate the bursts. The programmable features of burst length, burst sequence, and CAS latency enable further advantages. The device is available in 8-bit, 16-bit, and 32-bit data word sizes. Input data is registered on the I/O pins on both edges of Data Strobe signal(s), while output data is referenced to both edges of Data Strobe and both edges of CLK. ISSI 512-Mbit DDR SDRAM commands are registered on the positive edges of CLK.

IS43R32800D 8Mx32 256-Mbit DDR SDRAM

ISSI IS43R32800D 8Mx32 256-Mbit DDR SDRAM achieves high-speed data transfer using pipeline architecture and two data word accesses per clock cycle. The 268,435,456-bit memory array is internally organized as four banks of 64MB to allow concurrent operations. The pipeline allows Read and Write burst accesses to be virtually continuous, with the option to concatenate or truncate the bursts. The programmable features of burst length, burst sequence, and CAS latency enable further advantages.

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