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IM2G08D2DBBG-25

Name: Intelligent Memory IM2G08D2DBBG-25
Brand: Intelligent Memory
SKU: 822-IM2G08D2DBBG-25
Price: 28.37 USD
Availability: InStock

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Mouser No:

822-IM2G08D2DBBG-25

Mfr. No:

IM2G08D2DBBG-25

Mfr.:

Intelligent Memory

Description:

DRAM DDR2 2Gb, 1.8V, 256Mx8, 400MHz (800Mbps), 0C to +95C, FBGA-60

Datasheet:

IM2G08D2DBBG-25 Datasheet

ECAD Model:

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Learn more about Intelligent Memory IM2G08D2DBBG-25

In Stock: 374

Stock:: 374 Can Dispatch Immediately

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Factory Lead Time:: 26 Weeks Estimated factory production time for quantities greater than shown.

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Pricing (USD)

Qty.	Unit Price	Ext. Price
	$28.37	$28.37
	$26.26	$262.60
	$25.42	$635.50
528	Quote

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Product Attribute	Attribute Value	Select Attribute
Manufacturer:	Intelligent Memory
Product Category:	DRAM
RoHS:
Type:	SDRAM - DDR2
Memory Size:	2 Gbit
Data Bus Width:	8 bit
Maximum Clock Frequency:	400 MHz
Package/Case:	FBGA-60
Organisation:	256 M x 8
Access Time:	400 ps
Supply Voltage - Min:	1.7 V
Supply Voltage - Max:	1.9 V
Minimum Operating Temperature:	0 C
Maximum Operating Temperature:	+ 95 C
Series:	IM2G08D2
Packaging:	Tray
Brand:	Intelligent Memory
Country of Assembly:	Not Available
Country of Diffusion:	Not Available
Country of Origin:	TW
Moisture Sensitive:	Yes
Mounting Style:	SMD/SMT
Product Type:	DRAM
Factory Pack Quantity:	264
Subcategory:	Memory & Data Storage
Supply Current - Max:	58 mA
Unit Weight:	187 mg

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Datasheet

IM2G08D2DBBG-25 Datasheet

CNHTS:: 8542329010
CAHTS:: 8542320020
USHTS:: 8542320036
MXHTS:: 8542320299
ECCN:: EAR99

Dynamic Random Access Memory (DRAM)

Intelligent Memory Dynamic Random Access Memory (DRAM) includes a full range of JEDEC-compliant DRAMs and ECC DRAMs (SDRAM, DDR, DDR2, DDR3, DDR4, LPDDR4). From an application's point of view, these components work like a monolithic device. The DRAM devices allow for maximum levels of memory density without altering existing board layouts or designs.

Double Data Rate 2 (DDR2) SDRAM

Intelligent Memory Double Data Rate (DDR2) Synchronous DRAM (SDRAM) are eight-bank devices that achieve high-speed data transfer rates. Interleaving the eight memory banks allows random access operations faster than standard DRAMs. A chip architecture prefetches multiple bits and then synchronizes the output data to a system clock. All control, address, and circuits are synchronized with the positive edge of an externally supplied clock. In a source-synchronous manner, I/Os are synchronized with a pair of bidirectional strobes. A sequential, gapless data rate is possible depending on the device's burst length, CAS latency, and speed grade.