IME1G16D2DEBG-25I

Intelligent Memory
822-IME1G16D2DEBG25I
IME1G16D2DEBG-25I

Mfr.:

Description:
DRAM ECC DDR2, 1Gb, 1.8V, 64Mx16, 400MHz (800Mbps), -40C to +95C, FBGA-84

Datasheet:
ECAD Model:
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Learn more about Intelligent Memory IME1G16D2DEBG-25I

In Stock: 86

Stock:
86 Can Dispatch Immediately
Factory Lead Time:
26 Weeks Estimated factory production time for quantities greater than shown.
Minimum: 1   Multiples: 1
Unit Price:
$-.--
Ext. Price:
$-.--
Est. Tariff:

Pricing (USD)

Qty. Unit Price
Ext. Price
$15.37 $15.37
$14.27 $142.70
$13.84 $346.00
$13.51 $675.50
$13.17 $1,317.00
$12.74 $2,662.66
$12.42 $5,191.56
1,045 Quote

Product Attribute Attribute Value Select Attribute
Intelligent Memory
Product Category: DRAM
RoHS:  
SDRAM - DDR2
1 Gbit
16 bit
400 MHz
FBGA-84
64 M x 16
400 ps
1.7 V
1.9 V
- 40 C
+ 95 C
IME1G16D2
Tray
Brand: Intelligent Memory
Country of Assembly: Not Available
Country of Diffusion: Not Available
Country of Origin: TW
Moisture Sensitive: Yes
Mounting Style: SMD/SMT
Product Type: DRAM
Factory Pack Quantity: 209
Subcategory: Memory & Data Storage
Supply Current - Max: 80 mA
Unit Weight: 189 mg
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Attributes selected: 0

Datasheet

CAHTS:
8542320020
USHTS:
8542320032
MXHTS:
8542320299
ECCN:
EAR99

Dynamic Random Access Memory (DRAM)

Intelligent Memory Dynamic Random Access Memory (DRAM) includes a full range of JEDEC-compliant DRAMs and ECC DRAMs (SDRAM, DDR, DDR2, DDR3, DDR4, LPDDR4). From an application's point of view, these components work like a monolithic device. The DRAM devices allow for maximum levels of memory density without altering existing board layouts or designs.

Double Data Rate 2 (DDR2) SDRAM

Intelligent Memory Double Data Rate (DDR2) Synchronous DRAM (SDRAM) are eight-bank devices that achieve high-speed data transfer rates. Interleaving the eight memory banks allows random access operations faster than standard DRAMs. A chip architecture prefetches multiple bits and then synchronizes the output data to a system clock. All control, address, and circuits are synchronized with the positive edge of an externally supplied clock. In a source-synchronous manner, I/Os are synchronized with a pair of bidirectional strobes. A sequential, gapless data rate is possible depending on the device's burst length, CAS latency, and speed grade.

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