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CD74ACT164BQAR

Name: Texas Instruments CD74ACT164BQAR
Brand: Texas Instruments
SKU: 595-CD74ACT164BQAR
Price: 0.89 USD
Availability: InStock

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Mouser No:

595-CD74ACT164BQAR

Mfr. No:

CD74ACT164BQAR

Mfr.:

Texas Instruments

Description:

Counter Shift Registers 8-Bit Serial-In/Para llel-Out Shift Regi

Lifecycle:

New Product:

New from this manufacturer.

Datasheet:

CD74ACT164BQAR Datasheet

ECAD Model:

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More Information

Learn more about Texas Instruments CD74ACT164BQAR

In Stock: 2,950

Stock:: 2,950 Can Dispatch Immediately

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Factory Lead Time:: 12 Weeks Estimated factory production time for quantities greater than shown.

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Ext. Price:

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Pricing (USD)

Qty.	Unit Price	Ext. Price
	$0.89	$0.89
	$0.639	$6.39
	$0.576	$14.40
	$0.507	$50.70
	$0.473	$118.25
	$0.453	$226.50
	$0.452	$452.00
Full Reel (Order in multiples of 3000)
	$0.416	$1,248.00
	$0.406	$2,436.00

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Product Attribute	Attribute Value	Select Attribute
Manufacturer:	Texas Instruments
Product Category:	Counter Shift Registers
RoHS:
Number of Bits:	8 bit
Package/Case:	WQFN-14
Number of Input Lines:	4 Input
Output Type:	Push Pull
Propagation Delay Time:	157 ns
Supply Voltage - Min:	4.5 V
Supply Voltage - Max:	5.5 V
Minimum Operating Temperature:	- 55 C
Maximum Operating Temperature:	+ 125 C
Packaging:	Reel
Packaging:	Cut Tape
Brand:	Texas Instruments
Country of Assembly:	Not Available
Country of Diffusion:	Not Available
Country of Origin:	CN
High Level Output Current:	- 24 mA
Input Type:	TTL
Low Level Output Current:	24 mA
Mounting Style:	SMD/SMT
Number of Output Lines:	8 Output
Operating Supply Voltage:	4.5 V to 5.5 V
Product:	Shift Registers
Product Type:	Counter Shift Registers
Series:	CD74ACT164
Factory Pack Quantity:	3000
Subcategory:	Logic ICs

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Datasheet

CD74ACT164BQAR Datasheet

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CNHTS:: 8542399000
USHTS:: 8542390090
TARIC:: 8542319000
MXHTS:: 8542399999
ECCN:: EAR99

CD74AC164/CD74ACT164 8-Bit SIPO Shift Registers

Texas Instruments CD74AC164/CD74ACT164 8-Bit SIPO Shift Registers have two serial inputs (A and B) connected through an AND gate and an asynchronous clear (CLR). The device requires a high signal on both A and B to set the input data line high; a low signal on either will set the input data line low. Data at A and B can be changed while CLK is high or low, provided the minimum set-up time requirements are met.