SN74ACT2G100PWR

Texas Instruments
595-SN74ACT2G100PWR
SN74ACT2G100PWR

Mfr.:

Description:
Flip-Flops Dual-channel 2V-to-6 V multiple-function

Lifecycle:
New Product:
New from this manufacturer.
Datasheet:
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Availability

Stock:
0

You can still purchase this product for backorder.

Factory Lead Time:
18 Weeks Estimated factory production time for quantities greater than shown.
Minimum: 1   Multiples: 1
Unit Price:
$-.--
Ext. Price:
$-.--
Est. Tariff:
Packaging:
Full Reel (Order in multiples of 3000)

Pricing (USD)

Qty. Unit Price
Ext. Price
Cut Tape / MouseReel™ †
$0.44 $0.44
$0.306 $3.06
$0.273 $6.83
$0.237 $23.70
$0.219 $54.75
$0.209 $104.50
$0.201 $201.00
Full Reel (Order in multiples of 3000)
$0.189 $567.00
$0.184 $1,104.00
† A MouseReel™ fee of $7.00 will be added and calculated in your basket. All MouseReel™ orders are non-cancellable and non-returnable. ↩

Product Attribute Attribute Value Select Attribute
Texas Instruments
Product Category: Flip-Flops
RoHS:  
D-Type Rising Edge Flip Flop
74ACT
Non-Inverted
TSSOP-16
SchmittTrigger
10.4 ns
- 24 mA
24 mA
4.5 V
5.5 V
SMD/SMT
- 40 C
+ 125 C
Reel
Cut Tape
MouseReel
Brand: Texas Instruments
Country of Assembly: Not Available
Country of Diffusion: Not Available
Country of Origin: Not Available
Maximum Clock Frequency: 150 MHz
Number of Input Lines: 8 Input
Number of Output Lines: 2 Output
Product Type: Flip Flops
Series: SN74ACT2G100
Factory Pack Quantity: 3000
Subcategory: Logic ICs
Triggering Type: Positive Edge
Unit Weight: 67 mg
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Attributes selected: 0

Datasheet

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USHTS:
8542390090
TARIC:
8542319000
ECCN:
EAR99

SN74ACT2G100/SN74ACT2G100-Q1 Flip-Flops

Texas Instruments SN74ACT2G100/SN74ACT2G100-Q1 Flip-Flops contain two independent D-type flip-flops with rising-edge-triggered clock, active-low clear, and configurable logic data inputs. The data inputs can be configured for multiple 1- and 2-input logic functions, including buffer, inverter, AND, OR, NAND, NOR, XOR, and XNOR. All inputs on the TI SN74ACT2G100/SN74ACT2G100-Q1 Flip-Flops have a Schmitt-trigger architecture to support slow or noisy input signals. 

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